Contact us



PRBS generation 128 bits at a time

But what if we want to run faster than the FPGA clock and produce multiple bits per clock cycle that may be fed into a mux for higher data rates or if we just need more than one bit per clock for whatever we're doing. This time we're using a PN31.

module prbs_wide_generate (
   // Outputs
   // Inputs
   clk, reset

  parameter         WIDTH = 128,
                  PN = 7,//not used but good to know
                  TAP1 = 30,
                  TAP2 = 27;

   output [WIDTH-1:0] prbs;
   input               clk, reset;

   reg [WIDTH-1:0]        prbs;
   reg [WIDTH-1:0]    d;//d is a temp variable

   always @ (posedge clk)
     if (reset)
       prbs <= 1; //anything but teh all 0s case is fine.
          d = prbs; //blocking assignment used on purpose here
          repeat (WIDTH) d = {d,d[TAP1]^d[TAP2]};//again blocking is intentional
          prbs <= d;
       end // else: !if(reset)
endmodule // prbs_wide_generate

There are a few things to note in this code. Even though the PN31 only needs 31 bits of state, we need to have a much wider register to store the old state because we're calculating from much older bits than just the past 31. More confusing is the use of blocking assignments. The few lines of code between the begin end use both blocking and blocking. The idea is to have the complete 128 bits calculated all in one clock cycle. I like to think of it as spinning the generator 128 times per clock cycle. If we used non-blocking assignments, we would only have one rotation per clock cycle. This way, the current state is transferred to 'd', spun 128 times, and then transferred back to 'prbs'. Note you may get a warning on the register 'd' because it optimizes out in synthesis.